The present invention relates to flash memories and, more particularly, to a method of managing a flash memory whose cells can be programmed with more than one bit each.
Flash memory devices have been known for many years. Typically, each cell within a flash memory stores one bit of information. Traditionally, the way to store a bit has been by supporting two states of the cell—one state represents a logical “0” and the other state represents a logical “1”. In a flash memory cell the two states are implemented by having a floating gate above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within this floating gate. Typically, one state is with zero charge in the floating gate and is the initial unwritten state of the cell after being erased (commonly defined to represent the “1” state) and another state is with some amount of negative charge in the floating gate (commonly defined to represent the “0” state). Having negative charge in the gate causes the threshold voltage of the cell's transistor (i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct) to increase. Now it is possible to read the stored bit by checking the threshold voltage of the cell—if the threshold voltage is in the higher state then the bit value is “0” and if the threshold voltage is in the lower state then the bit value is “1”. Actually there is no reed to accurately read the cell's threshold voltage—all that is needed is to correctly identify in which of the two states the cell is currently located. For that purpose it suffices to make a comparison against a reference voltage value that is in the middle between the two states, and thus to determine if the cell's threshold voltage is below or above this reference value.
FIG. 1A shows graphically how this works. Specifically, FIG. 1A shows the distribution of the threshold voltages of a large population of cells. Because the cells in a flash device are not exactly identical in their characteristics and behavior (due, for example, to small variations in impurity concentrations or to defects in the silicon structure), applying the same programming operation to all the cells does not cause all of the cells to have exactly the same threshold voltage. (Note that, for historical reasons, writing data to a flash memory is commonly referred to as “programming” the flash memory. The terms “writing” and “programming” are used interchangeably herein.) Instead, the threshold voltage is distributed similar to the way shown in FIG. 1A. Cells storing a value of “1” typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the left peak of FIG. 1A, with some smaller numbers of cells having lower or higher threshold voltages. Similarly, cells storing a value of “0” typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the right peak of FIG. 1A, with some smaller numbers of cells having lower or higher threshold voltages.
In recent years a new kind of flash device has appeared on the market, using a technique conventionally called “Multi Level Cells” or MLC for short. (This nomenclature is misleading, because the previous type of flash cells also has more than one level: they have two levels, as described above. Therefore, the two kinds of flash cells are referred to herein as “Single Bit Cells” (SBC) and “Multi-Bit Cells” (MBC).) The improvement brought by the MBC flash is the storing of two bits in each cell. (In principle MBC also includes the storage of more than two bits per cell. In order to simplify the explanations, the two-bit case is emphasized herein. It should however be understood the present invention is equally applicable to flash memory devices that support more than two bits per cell.) In order for a single cell to store two bits of information the cell must be able to be in one of four different states. As the cell's “state” is represented by its threshold voltage, it is clear an MBC cell should support four different valid ranges for its threshold voltage. FIG. 1B shows the threshold voltage distribution for a typical MBC cell. As expected, FIG. 1B has four peaks, each corresponding to one of the states. As for the SBC case, each state is actually a range of threshold voltages and not a single threshold voltage. When reading the cell's contents, all that must be guaranteed is that the range that the cell's threshold voltage is in is correctly identified. For a prior art example of an MBC flash device see U.S. Pat. No. 5,434,825 to Harari.
When encoding two bits in an MBC cell as one of the four states, it is common to have the left-most state in FIG. 1B (typically having a negative threshold voltage) represent the case of both bits having a value of “1”. (In the discussion below the following notation is used—the two bits of a cell are called the “lower bit” and the “upper bit”. An explicit value of the bits is written in the form [“upper bit” “lower bit”], with the lower bit value on the right. So the case of the lower bit being “0” and the upper bit being “1” is written as “10”. One must understand that the selection of this terminology and notation is arbitrary, and other names and encodings are possible). Using this notation, the left-most state represents the case of “11”. The other three states are illustrated as assigned in the following order from left to right—“10”, “00”, “01”. One can see an example of an implementation of an MBC NAND flash device using such encoding as described above in U.S. Pat. No. 6,522,580 to Chen, which patent is incorporated by reference for all purposes as if fully set forth herein. See in particular FIG. 8 of the Chen patent. It should be noted though that the present invention does not depend on this assignment of the states, and there are other ordering that can be used. When reading an MBC cell's content, the range that the cell's threshold voltage is in must be identified correctly; only in this case this cannot always be achieved by comparing to one reference voltage, and several comparisons may be necessary. For example, in the case illustrated in FIG. 1B, one way to read the lower bit is first to compare the cell's threshold voltage to a reference comparison voltage V1 and then, depending on the outcome of the comparison, to compare the cell's threshold voltage to either a zero reference comparison voltage or a reference comparison voltage V2. Another way to read the lower bit is to compare the cell's threshold voltage unconditionally to both the zero reference voltage and V2. In either case, two comparisons are needed.
MBC devices provide a great advantage of cost—using a similarly sized cell one stores two bits rather than one. However, there are also some drawbacks to using MBC flash—the average read and write times of MBC memories are longer than of SLC memories, resulting in lower performance. Also, the reliability of MBC is lower than SBC. This can easily be understood—the differences between the threshold voltage ranges in MBC are much smaller than in SBC. Thus, a disturbance in the threshold voltage (e.g. leaking of the stored charge causing a threshold voltage drift, interference from operations on neighboring cells, etc.) that may have gone unnoticed in SBC because of the large gap between the two states, might cause an MBC cell to move from one state to another, resulting in an erroneous bit. The end result is a lower quality specification of MBC cells in terms of data retention time or the endurance of the device to many write/erase cycles. Thus there are advantages to using both MBC cells and SBC cells, and the selection can be different depending on the application's requirements.
The most common type of data storage flash memory is the NAND type, so called because of the architecture by which its cells are internally connected. In NAND flash writing operations may only be done for relatively large chunks of data (typically 512 bytes to 2 Kilobytes), and not for single bytes or small groups of bytes. The smallest data chunk that can be independently written in such devices is called a “page”. Reading operations are also done in units of pages, in the sense that a full page is always retrieved from the array of cells into a RAM buffer in the flash device. In many MBC NAND flash devices the two or more bits that share a memory cell are assigned to different respective pages. For example, in a two-bit-cell MBC device, the lower bit of a cell may belong to page number zero, while the upper bit of the cell belongs to page number one (or, more generally, the lower bit of a cell may belong to page number 2n while the upper bit of the cell belongs to page 2n+1).
One side-effect detected in MBC NAND flash devices with cells shared across multiple pages as described above is that, unlike in SBC flash devices, the programming time of a page of memory varies between different pages and is not the same for all pages. This can be understood by referring to FIG. 1B showing one example of the encoding of the bits in a two-bit MBC cell. When writing the lower bit into a cell, we either do nothing (when the written bit is “1”) or we shift the state from “11” to “10” (when the written bit is “0”). Then when writing the upper bit into the cell, we either do nothing (if the written bit is “1”) or we shift the state from “10” to “00” (if both lower and upper bits are “0”) or we shift the state from “11” to “01” (if the lower bit was “1” and the upper bit is “0”). The shift of threshold voltage when writing the upper (second) bit may be much larger than the shift when writing the lower (first) bit. In the former case we may need to shift the cell from the left-most state to the right-most state (that is—from “11” to “01”), while in the latter case the most we do is to shift the cell one “position” (from “11” to “10”). Shifting the state (that is—the cell's threshold voltage) over larger distances requires more programming pulses and therefore more time. Therefore it is indeed to be expected that in devices implemented according to the above example programming page zero (which uses lower bits) will be faster than programming page one (which uses upper bits).
A similar effect occurs for reading. In the above example, reading an upper bit from a cell can be done by one comparison only—distinguishing between the two leftmost states (“11” and “10”) and the two right-most states (“00” and “01”), while reading a lower bit requires two comparisons. Therefore it should be expected that in devices implemented according to the above example, reading of page zero (which uses lower bits) will be slower than reading page one (which uses upper bits).
Data sheets of MBC NAND devices do not usually disclose this fact of dependency of write and read operations time on page number. One may look as an example at the data sheet of the TC58NVG2D4BFT00 MBC 4 Gbit NAND flash device of Toshiba Corporation. The data sheet only specifies “average” or “typical” values for programming time and reading time. But when one runs actual tests on this device one can easily detect the dependency exactly as predicted in the above example—even-numbered pages are faster to write and slower to read, and odd-numbered pages are slower to write and faster to read. Indeed in this Toshiba device the write time of even-numbered pages and the read time of odd-numbered pages are close to the corresponding times in corresponding SBC devices of the same process generation. This is not true in all devices, but it is quite a typical case.
One should understand that this specific behavior pattern is not necessarily the case for all devices—other devices might use different bit encoding schemes for their cells' states and their page-dependency pattern might be different. For example there may be flash devices where the even-numbered pages are slower to write and faster to read, and odd-numbered pages are faster to write and slower to read. There may be flash devices in which the first two out of each aligned group of four pages have a performance pattern different from the performance pattern of the last two pages of that group. There may be flash devices in which the rule to find out whether a given page has a certain read or write performance characteristic is quite complex, but as long as the MBC NAND device architecture is such that cells are shared across multiple pages, it always is the case that not all pages have the same write time and read time.
It is obvious that a cell designed for MBC operation should also be able to operate as an SBC cell. After all, two states are just a subset of four states. Indeed, this idea already has appeared in the prior art—see for example U.S. Pat. No. 6,426,893, to Conley et al., that is incorporated by reference for all purposes as if fully set forth herein, wherein it is proposed to use both MBC and SBC modes within the same device, selecting certain parts of the device to operate with highest density in MBC mode, while other parts are used in SBC mode and provide better performance.
Other prior art goes even further—deciding on the mode a specific flash block operates in (whether MBC or SBC) dynamically during an application's run-time. For example, U.S. Pat. No. 5,930,167 to Lee et al., that also is incorporated by reference for all purposes as if fully set forth herein, describes a system in which incoming data
According to the present invention there is provided a method of using a flash memory that includes at least one block, each block including a first plurality of pages and a second plurality of pages, the first plurality of pages having faster write access than the second plurality of pages, the method including the steps of: (a) writing first data to a first page of the first plurality of pages of one of the at least one block; and (b) skipping at least one page of the second plurality of pages of the one block to write second data to a second page of the first plurality of pages of the one block.
According to the present invention there is provided a memory device, for storing data, including: (a) a flash memory that includes at least one block, each block including a first plurality of pages and a second plurality of pages, the first plurality of pages having faster write access than the second plurality of pages; and (b) a controller operative: (i) to write first data to a first page of the first plurality of pages of one of the at least one block, and (ii) to skip at least one page of the second plurality of pages of the one block to write second data to a second page of the first plurality of pages of the one block.
According to the present invention there is provided a system, for storing data, including: (a) a memory device that includes a flash memory that includes at least one block, each block including a first plurality of pages and a second plurality of pages, the first plurality of pages having faster write access than the second plurality of pages; and (b) a processor operative: (i) to write first data to a first page of the first plurality of pages of one of the at least one block, and (ii) to skip at least one page of the second plurality of pages of the one block to write second data to a second page of the first plurality of pages of the one block.
According to the present invention there is provided a computer readable storage medium having computer readable code embodied on the computer readable storage medium, the computer readable code for managing a flash memory that includes at least one block, each block including a first plurality of pages and a second plurality of pages, the first plurality of pages having faster write access than the second plurality of pages, the computer readable code including: (a) program code for writing first data to a first page of the first plurality of pages of one of the at least one block; and (b) program code for skipping at least one page of the second plurality of pages of the one block to write second data to a second page of the first plurality of pages of the one block.
According to the present invention there is provided a method of using a flash memory that includes a plurality of blocks, each block including a first plurality of pages and a second plurality of pages, the first plurality of pages having faster write access than the second plurality of pages, the method including the steps of: (a) writing first data to a first page of the first plurality of pages of a first block; (b) skipping at least one page of the second plurality of pages of the first block to write second data to a second page of the first plurality of pages of the first block; and (c) copying the first and second data to at least one page of the first plurality of pages of a second block other than the first block and to at least one page of the second plurality of pages of the second block.
According to the present invention there is provided a method of using a flash memory that includes at least one block, each block including a first plurality of pages and a second plurality of pages, the first plurality of pages having faster read access than the second plurality of pages, the method including the steps of: (a) writing first data to a first page of the first plurality of pages of one of the at least one block; and (b) skipping at least one page of the second plurality of pages of the one block to write second data to a second page of the first plurality of pages of the one block.
According to the present invention there is provided a memory device, for storing data, including: (a) a flash memory that includes at least one block, each block including a first plurality of pages and a second plurality of pages, the first plurality of pages having faster read access than the second plurality of pages; and (b) a controller operative: (i) to write first data to a first page of the first plurality of pages of one of the at least one block, and (ii) to skip at least one page of the second plurality of pages of the one block to write second data to a second page of the first plurality of pages of the one block.
According to the present invention there is provided a system, for storing data, including: (a) a memory device that includes a flash memory that includes at least one block, each block including a first plurality of pages and a second plurality of pages, the first plurality of pages having faster read access than the second plurality of pages; and (b) a processor operative: (i) to write first data to a first page of the first plurality of pages of one of the at least one block, and (ii) to skip at least one page of the second plurality of pages of the one block to write second data to a second page of the first plurality of pages of the one block.
According to the present invention there is provided a method of using a flash memory that includes a plurality of blocks, each block including a first plurality of pages and a second plurality of pages, the first plurality of pages having faster read access than the second plurality of pages, the method including the steps of: (a) writing first data to a first page of the first plurality of pages of a first block; (b) skipping at least one page of the second plurality of pages of the first block to write second data to a second page of the first plurality of pages of the first block; and (c) writing third data to both at least one page of the first plurality of pages of a second block other than the first block and to at least one page of the second plurality of pages of the second block.
According to the present invention there is provided a computer readable storage medium having computer readable code embodied on the computer readable storage medium, the computer readable code for managing a flash memory that includes at least one block, each block including a first plurality of pages and a second plurality of pages, the first plurality of pages having faster read access than the second plurality of pages, the computer readable code including: (a) program code for writing first data to a first page of the first plurality of pages of one of the at least one block; and (b) program code for skipping at least one page of the second plurality of pages of the one block to write second data to a second page of the first plurality of pages of the one block.
The present invention is directed towards methods and systems for writing data to a flash memory and towards computer-readable storage media that bear code for implementing the methods. Specifically, the present invention is directed towards flash memories whose blocks include two kinds of pages: pages with relatively fast write access or read access speeds and pages with relatively slow write access or read access speeds. Generally, an application running on a host of the memory writes more than one page's worth of data to a block of the memory. The general concept of the present invention is, after writing data to a fast access page, to skip one or more slow access pages and to continue writing data to another fast access page.
In the appended claims, the fast-access page that is written to before skipping the slow access pages is called the “first” fast-access page, the data written to that page are called “first” data, the fast-access page that is written to after skipping the slow-access pages is called the “second” fast-access page, and the data written to that page are called “second” data. The terms “first page” and “second page”, as used in the appended claims, therefore do not imply that the “first page” is the first page of the block and that the “second page” is the second page of the block, or even that the “second page” is the second fast-access page of the block. For example, in some flash memories, the fast-access pages and the slow-access pages alternate within the blocks: if the pages of a block are numbered starting from zero, the even-numbered pages are fast-access pages and the odd-numbered pages are slow-access pages. Then if writing starts from page 0, page 1 is skipped and writing resumes at page 2, so that page 0 is the “first page” and page 2 is the “second page”. In other flash memories, pairs of fast-access pages and slow-access pages alternate within the blocks: if the pages of a block are numbered starting from zero, the pages numbered 4n and 4n+1 are fast-access pages and the pages numbered 4n+2 and 4n+3 are slow-access pages. Then if writing starts from page 0, pages 2 and 3 are skipped and writing resumes from page 4. Either page 0 or page 1 can be considered the “first page”, and page 4 is the “second page”.